On-chip inductors have widespread applications in radiofrequency integrated circuits (RFICs). Planar spiral inductors are the most commonly used on-chip inductors in current RFIC designs due to ease of fabrication with standard CMOS processes, which, at the same time, limit the design to a two-dimensional (2D) wafer surface. Conventional planar spiral inductors utilize self and mutual electromagnetic coupling of long parallel wires to achieve high inductance. For example, a 10 nH planar spiral inductor usually takes up to about 400×400 μm2 on-wafer area with a typical maximum quality (Q) factor of about 6 at frequencies lower than 3 GHz and a self-resonance frequency of about 10 GHz. The large footprint introduces significant parasitic coupling capacitance and ohmic loss from the substrate, which are the two main reasons for the low Q factor and resonance frequency.
Efforts have been made for a long time to shrink the size and maintain or improve the performance of on-chip planar spiral inductors. For example, stacked planar spiral inductors were reported to occupy an area about 16% of that of conventional ones at a similar value of inductance. Suspended MEMS spiral inductors with a Q factor as high as 20 at a frequency over 10 GHz have been demonstrated. Three dimensional (3D) spiral coil inductors, with a tunable inductance independent of their base dimensions, have been shown to have a Q factor as high as 17 through metal deformation driven by thermal stress. Intel achieved high Q factors greater than 20 using planar inductors having a footprint compatible with the 32 nm and beyond system on chip (SoC) platform, but had to resort to a very thick, low-resistivity top metal layer (4-7 μm). All of these approaches addressed only some aspects of the shortcomings of planar spiral inductors.